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GMDSS: Element 3

Question 211 of 605

For the logic input levels shown in Figure 3E12, what are the logic levels of test points A, B and C in this circuit? (Assume positive logic.)

USCG illustration 3E12 for GMDSS Element 3 question 211 — Illustration 3E12

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More Element 3 questions

#209 Which of the following logic gates will provide an active high out when both inputs are active high?
#210 In a negative-logic circuit, what level is used to represent a logic 0?
#212 For the logic input levels given in Figure 3E13, what are the logic levels of test points A, B and C in this circuit? (A...
#213 In a positive-logic circuit, what level is used to represent a logic 1?
#214 Given the input levels shown in Figure 3E14 and assuming positive logic devices, what would the output be?

3E12

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